The consumer market is very aggressive and in high-speed new product versions are introduced to the market. Being on time and with the promised feature set is extremely important. Failure to meet agreed timescales can result in the supplier being barred for the next year. One of the reasons that the release of a new model can be delayed is when late in the development process it is discovered that the required features cannot run or perform suitably on the hardware platform. Handcrafting of the design or a reduction in functionality is often the only acceptable short term solution. It is crucial that critical deadlines, speed, effectiveness and determinism of development process are realized.


Introducing system level modelling can significantly reduce the risk of unexpected feature interaction, performance bottlenecks and resource limitations being discovered late in the development process. Architects can model critical use cases running on new silicon prior to full implementation and subsequent testing. High level system modelling and analysis of complex HW/SW can provide a significant productivity boost and de-risking of new developments. The goals of the Anaconda 2013 project were as follows:

  • Methods for real-time early phase design analysis
  • Model-based design validation with focus on system performance and resource usage concerns
  • Prediction of performance behaviour of a growing application stack on SOCs and Operating Systems
  • Impact analysis of software and hardware building blocks and processing architectures.

The Anaconda resulted in a model-driven design approach based on generating analysis models from consumer electronic systems (with a first application on smart-TV) described in Domain Specific Languages (DSLs) that conform to a Y-chart modelling style. The analysis models exploit basic algorithms, Microsoft Excel workbooks, dataflow models and the Parallel Object-Oriented Specification Language (POOSL). Using these approaches, Anaconda shared its results with other projects at TNO-ESI with, amongst others, ASML, Philips Healthcare, Océ Technologies, Vanderlande Industries and NXP, thereby generalizing and disseminating the TNO-ESI knowledge base on Y-chart styled performance models for design-space exploration and bottleneck identification.


Industrial partner TP vision
Knowledge partner TNO-ESI

Project status

Roadmap HTSM Embedded Systems
Project finished 2013

Frans Beenker

Business Director
+31 (0)88 866 54 20